Abandon 4F², mass production of HBM4, G11 NAND speed up... Micron (MU.US) unveils roadmap at technology seminar, JPMorgan maintains "Overweight" rating

According to a recent report from Zhitong Finance APP, J.P. Morgan's latest research note highlighted that Micron Technology (MU.US) provided a detailed demonstration of its latest technological innovations and long-term plans for its three core product lines—DRAM, HBM, and NAND—at the investor technology webinar held on October 21. The analyst team led by Harlan Sur believes that Micron’s technology roadmap is clear and forward-looking, and the company is well positioned to continue benefiting from the AI-driven boom in memory demand. As a result, they maintain an “Overweight” rating on the stock.

Sticking to the 6F² DRAM Architecture While Pursuing 3D DRAM Development in Parallel

J.P. Morgan’s report pointed out that in terms of DRAM architecture evolution, Micron gave a clear response to the industry debate over the 6F² versus 4F² technical routes. Micron stated that the next generation of DRAM nodes will continue to adopt the 6F² architecture, rather than 4F². The company is confident in maintaining its leadership in power consumption and performance through aggressive node scaling, process innovation, and product-level optimization.

Micron revealed that it has conducted research on 4F² DRAM for about 20 years, but ultimately decided not to adopt it—mainly because its process is more complex and costly, and the company believes the benefits from scaling are limited.

J.P. Morgan detailed three major challenges faced by the 4F² architecture in manufacturing: First, it requires denser deposition and etching processes, which significantly increases the probability of yield issues; second, 4F² imposes stricter process tolerances (such as overlay and alignment), putting additional pressure on manufacturability and yield; lastly, the architecture is susceptible to the “Floating Body Effect,” where charges get trapped in the transistor channel, resulting in performance degradation and leakage issues.

In addition, Micron disputed the notion that 4F² is more advantageous than 6F² in terms of density, emphasizing that DRAM bit density is ultimately determined by the capacitor pitch rather than the underlying interconnect pitch.

According to the current roadmap, Micron will continue to use the planar architecture based on 6F² for the next few generations of DRAM nodes (expected to last until 2030), while developing 3D DRAM technology in parallel.

HBM Roadmap Broadens, Customization and Vertical Stacking Become Focal Points

In the highly watched HBM field, Micron disclosed that HBM4 has entered mass production with smooth ramp-up progress, while the next generation HBM4E is on the roadmap and samples are being sent to key customers this year.

Looking ahead, Micron expects standard HBM and custom HBM products to coexist for the long term. Custom HBM integrates memory IP and logic IP into the base die, enabling deeper collaboration on customer-specific designs. The Micron team pointed out that both standard JEDEC HBM and custom HBM products will use foundry nodes in the future. For HBM4E, with higher requirements for speed, power, and functionality, more advanced CMOS processes will be needed.

Beyond standard and custom HBM, Micron also highlighted two important long-term memory architectures: vertical HBM and vertical edge inference memory (vEIM). Vertical HBM places memory directly above the processor to shorten the storage-to-compute path, providing significant bandwidth improvements; vEIM uses a similar approach but is specifically optimized for low-power edge AI inference use cases (vertical HBM focuses on high bandwidth, while vEIM focuses on low power consumption).

Micron emphasized that hybrid bonding, higher stack counts, advanced thermal management, and customer co-design have become increasingly prominent in the HBM roadmap. However, with the development of HBM, vertical HBM, and vEIM, these products require more wafers compared to standard DRAM, meaning the wafer-to-bit output conversion ratio will remain under pressure.

NAND Leaps Directly to G11 Generation, AI-grade Products Expand Market Potential

In the NAND sector, after leading the industry with three consecutive nodes from G7 to G9, Micron will leapfrog directly to the G11 node optimized for AI workloads. Compared with G9, G11 aims to deliver about double the bit density, up to 1.5x improvement in I/O speed, more than 25% reduction in per-bit energy consumption, and stack more than 400 layers.

The G11 node also marks Micron’s formal introduction of wafer-to-wafer bonding technology in NAND manufacturing. The company estimates that G11 will ramp up in the second half of 2027 and plans to disclose more details next year. Beyond G11, Micron also plans to continue scaling by introducing new materials and denser cell architectures.

At the product level, Micron is developing two types of AI-grade NAND products: one is a high-speed SLC-based design offering 25 million to 100 million IOPS, intended for GPU tasks such as vector search and AI context retrieval requiring extraction of massive small data blocks; the second uses TSV to stack NAND dies on top of a logic chip, enabling model weights, long contexts, and KV cache to be placed closer to the accelerator (but not right next to the GPU, as Micron believes there is no advantage). Given its higher cost, Micron is co-developing the second product with customers, and the eventual market share between the two offerings will depend on end-user markets.

For data center SSDs, Micron is the first manufacturer to mass-produce PCIe Gen6 SSDs and ship 245TB drives. Cost advantages from advanced nodes are expected to support further growth in high-capacity drives. J.P. Morgan believes that Micron’s NAND roadmap positions it well to fully benefit from AI-driven storage demand growth, with the potential to maintain or expand its top-three global enterprise SSD (eSSD) market share.

Deepening Customer Collaboration and Long-Cycle R&D, AI Tools Sharply Improve Efficiency

Micron elaborated on significant changes to its customer collaboration model. Compared to three or four years ago, engagement now begins at the conceptual stage and continues through co-design, qualification, and mass production—including custom projects with several cloud service providers (CSPs). For example, Micron is customizing LPDDR6 for Meta (META.US) for data center deployments; Weka has evolved from a Micron Ventures portfolio company into a business partner.

For R&D, Micron’s long-term investment spans three timeframes: first, a commitment to invest $550 million in Micron Ventures over the next 3 to 10 years; second, a 5-10 year collaboration with Albany NanoTech/NY CREATES to develop a high numerical aperture (High-NA) EUV and lithography roadmap for DRAM; and third, the $1 billion Micron Research Lab announced this summer, focused on cycles of more than 10 years.

Additionally, Micron is deploying AI technology throughout the entire development process—from early research to wafer fab. Data shows that for its latest data center SSD controllers, AI-assisted chip design and verification halved tape-out times compared to the previous generation; AI-generated firmware, root cause analysis, and intelligent test selection shortened the path to data center SSD customer-ready silicon by 60%.

Micron aims to double the speed from innovation to high-volume manufacturing (HVM) and is deepening partnerships with suppliers in lithography, packaging/hybrid bonding, and thin-film processing. J.P. Morgan sees these efforts as critical to Micron’s ability to advance more projects in parallel.